Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

ABSTRACT

A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

RELATED APPLICATIONS

This utility application is a continuation of U.S. application Ser. No. 09/665,922, filed on Sep. 20, 2000 now U.S. Pat. No. 6,748,513.

FIELD OF THE INVENTION

The present invention relates generally to memory controllers. In particular, the present invention relates to an apparatus and method for a low latency source-synchronous address receiver for a system bus in a memory controller.

BACKGROUND OF THE INVENTION

Many computer devices operate based on an external clock. For example, a processor may receive a clock input and perform all operations or events only when the clock transitions. Devices in which events proceed based on a clock transition are referred to as “synchronous” devices.

Other computer devices do not base their operation on an external clock. These devices are referred to as “asynchronous” or “self-timed” devices. A self-timed device typically receives a request from a processor. The device then performs the operation and indicates to the processor when the operation is complete. However, the time required for the operation to complete is not based on an external clock (i.e., a predetermined number of clock cycles). Rather, in the case of a self-timed device, the time required is based on the asynchronous delay paths through the device, which may vary in duration based on the operations that are performed.

In a conventional memory controller architecture, the memory controller architecture generally includes a processor, a chipset and a main memory. A host system bus which connects the processor to the chipset is a synchronous device generally controlled by a common clock interface. In other words, the speed at which the host system bus can run is limited by the speed of the system clock. As technology pushes the processing speed, common clock interface buses run the risk of creating a bottleneck in memory controller architectures. In fact, these advances in processor design have pushed memory controller systems to a level where the speed of a bus or an architecture cannot be scaled using an increased clock frequency. One technique for accommodating the increased processor speed is to replace the host system bus with a source synchronous system bus.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, aspects, and advantages of the embodiments described herein will become more fully apparent from the following detailed description and appended claims when taken in conjunction with accompanying drawings in which:

FIG. 1 depicts a block diagram of a memory controller architecture system, in accordance with one embodiment;

FIG. 2 depicts a block diagram further illustrating the address receiver of FIG. 1, in accordance with one embodiment;

FIG. 3 depicts a timing diagram illustrating the functionality of the receiver as depicted in FIG. 2, in accordance with one embodiment;

FIG. 4 depicts a diagram of a source synchronous address receiver according to one embodiment;

FIG. 5 depicts a block diagram of a conventional memory controller architecture system according to one embodiment;

FIG. 6 depicts the source synchronous address receiver according to embodiment; and

FIG. 7 depicts a diagram illustrating the functionality of the source synchronous address receiver as depicted in FIG. 6, in accordance with one embodiment.

DETAILED DESCRIPTION OF THE INVENTION

An apparatus and method for a low latency source synchronous address receiver for a system bus in a memory controller are described. In one embodiment, a low latency path between a system bus address input to a memory bus is provided, resulting in a high performance memory controller by using a flow-through path. In one embodiment, flow-through path is controlled by two inputs: one is a source synchronous strobe directing the address receiver to latch an address and store it, while the other is a protocol signal that signals the beginning of an address transfer which enables the flow-through path.

In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments described herein. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. For example, various signals, layout patterns, memory cell configurations and circuits, and logic circuits may be modified according to the embodiments described herein. The following description provides examples, and the accompanying drawings show various examples for the purposes of illustration. However, these examples should not be construed in a limiting sense as they are merely intended to provide examples of the at least one embodiment, rather than to provide an exhaustive list of all possible implementations of the present invention. In some instances, well-known structures, devices, and techniques have not been shown in detail to avoid obscuring the present invention.

The following system architecture describes specific embodiments for implementing a double-pumped, source synchronous address receiver for a system bus. However, those skilled in the art will appreciate that the embodiments may be implemented using various circuit design modifications. Specifically, the flow-through path as taught by the present invention can be implemented using various logic design techniques while remaining within the scope of the embodiments described herein. Moreover, although one embodiment describes a two input, source synchronous address receiver, those skilled in the art will realize that the embodiments described herein can be easily extended to higher order interfaces by scaling the receiver structure.

In a conventional memory controller architecture, the memory controller generally includes a host system bus, which connects the processor to a chipset. Generally, the host system is controlled by a common clock interface. In other words, the speed at which the host bus can run is limited by the speed of the system clock. As technology pushes the processing speed of CPUs, common clock interface buses run the risk of creating a bottleneck in memory controller architectures. In fact, these advances in processor design have pushed memory controller systems to a level where the speed of a bus or an architecture cannot be scaled using an increased clock frequency.

Accordingly, in one embodiment, a memory controller architecture system 100 is provided using a source synchronous system bus 110. Representatively, system 100 comprises source synchronous processor system bus (front side bus (FSB)) 110 for communicating information between processor (CPU) 102 and chipset 104. As described herein, the term “chipset” is used in a manner to collectively describe the various devices coupled to CPU 102 to perform desired system functionality.

In one embodiment, chipset 104 includes a memory controller to communicate with main memory 106. In one embodiment, main memory 106 may include, but is not limited to, random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), Rambus DRAM (RDRAM) or any device capable of supporting high-speed buffering of data.

Representatively, chipset 104 may include an address receiver for receiving an address packet from CPU 110 in order to signal an address transaction request. Once the address packet is received by chipset 104, the chipset decodes the address packet 122 to generate an address of the requested data in main memory and return the requested data to the CPU. In one embodiment, address receiver 120 is further illustrated with reference to FIG. 2.

Representatively, address packet 122 may include a phase zero component (IFA[0]) 132, as well as phase one information (IFA[1]) 140. Unfortunately, phase zero information 132 of address packet 122 is vital for decoding of address packet 122 by chipset 104. Accordingly, a memory controller system, such as memory controller system 100 as depicted in FIG. 1, requires a low latency path between an address input of FSB 110 and memory bus 108 in order to achieve high performance unless phase zero address 132 can be instantly provided to core chipset logic 104. Once the address packet appears on an address pin, any benefits provided by using source synchronous FSB 110 are lost.

As depicted in FIG. 3, the address packet 122 includes a first component or phase zero component 132 and a second component or phase one component 140. The phase zero component 132 of the address packet 122 describes a transaction type of the address packet 122 (transaction address), indicating whether the address of the requested data is memory based or IO based. Consequently, this information is crucial to the memory controller architecture 100 for high-speed decoding of the address packet 122 by the chipset 104. The phase one component 140 of the address packet 122 contains address attributes of the address packet including data size/length attributes, byte enables, defer ID, extended functions, cycle types, etc. The information provided by the phase one component 140 of the address packet 122 is not as critical to the decoding stages as the phase zero component 114 of the address packet 112.

Referring again to FIG. 2, phase zero component 132 of the address packet 122 appears at an output 130 of first flip-flop 126 in response to the falling edge of strobe signal 124. Likewise, phase one component 140 of address packet 122 appears at an output 138 of the second flip-flop 134 in response to the rising edge of the strobe signal 124. Unfortunately, the address receiver 120 as depicted in FIG. 3 introduces a delay (TDA) 156, as indicated in the timing diagram, of as much as a few nanoseconds in producing the phase zero component 132 of the address packet 122 at the output 130 of the first flip-flop 126.

Accordingly, FIG. 4 depicts an embodiment illustrating a source synchronous address receiver (SSAR) 200 for use within a chipset memory controller system architecture, such as in a host system bus of a memory controller architecture 300 as depicted in FIG. 5. The source synchronous address receiver 200 includes an input differential amplifier 202 that compares an address packet 122 received on an address pin 204 for a data request against a reference voltage 206 to generate a digital address packet as the address packet 122. The address packet 122 includes a first, or phase zero component 132 (IFA[0]), describing a transaction type of the address packet 122 (transaction address) and a second, or phase one component 140 (IFA[1]), describing attributes of the address packet 122 as described above with reference to FIG. 3.

In one embodiment, flow-through circuit 220 receives a digital address strobe signal 210 and a digital address select signal 208. The digital address strobe signal 210 is a digital version of an analog source synchronous strobe signal 124 that directs the address receiver 200 to latch and store address information available on an address system bus such as the system bus 310. The digital address select signal 208 is generated from an analog common clock protocol signal 154 that signals the beginning of an address transfer and is used to enable a flow-through path as described below.

In one embodiment, flow-through circuit 220 generates an enable signal 240 in response to the digital address strobe signal 210 and the digital address select signal 208. The enable signal 240 is then provided to a flow-through gate 242 having the address packet as an input 244. The flow-through gate 242 provides the first or phase zero component 132 of the address packet 122 (transaction address) to a chipset, such as chipset 304, once the address packet 122 appears on the address pin 204. In one embodiment, the flow-through gate 242 provides a flow-through path from the address pin 204 to the chipset 304 for the transaction address 122 to expedite the initiation of decoding of the address packet 122 by the chipset 304. Representatively, first flip-flop 250 receives the digital address packet 122 and the digital address strobe signal 210 as inputs and provides the second or phase one component 140 of the address packet 122 to the chipset in response to the address strobe signal 208. Once the second, or phase one component 140, of the address packet 122 is provided to the chipset 304, the chipset 304 can complete decoding of the address packet 122.

FIG. 6 is a block diagram depicting the source synchronous address receiver 200 according to one embodiment. The flow-through circuit 220 further includes a second flip-flop 222, including a feedback inverter 224 coupled between an input 226 and an output 228 of the second flip-flop 222. The second flip-flop 222 also includes the digital address select signal 208 as a clock pulse input. A third flip-flop 230 also includes a feedback inverter 232 coupled between an input 234 and an output 236 of the third flip-flop 230. The third flip-flop 230 also includes the digital address strobe signal 210 as a clock pulse input. An exclusive-OR gate 238 includes the output of the second flip-flop 222 and the output of the third flip-flop 230 as inputs to generate the enable signal 240 for the flow-through gate 242.

In one embodiment, address receiver 200 also includes a first differential amplifier 260 that compares the analog common clock protocol signal 154, received on an address select pin 262, against the reference voltage 206 to generate a digital common clock protocol signal 264. A fourth flip-flop 266 receives the digital common clock protocol signal into signal 264 as an input 268 and a common clock signal (ABUTFCLK 100) as a clock pulse input 270. Once received, the fourth flip-flop 266 generates a flopped address select signal 216 at an output 272. An inverter 274 then receives the flopped address select signal 216 and generates the digital address select signal 208 at an output 276 of the inverter 274 for input to the flow-through circuit 220.

The source synchronous address receiver 200 also includes a second differential amplifier 280 that compares an analog address strobe signal 124 received on a address strobe pin 282 against the reference voltage 206 to generate the digital address strobe signal 210. In one embodiment, source-synchronous address receiver 200 is used for the system address bus 310 of the memory controller 300 as depicted in FIG. 5. In one embodiment, CPU 302 of the memory controller 300 is preferably a Willamette® generation CPU as manufactured by the Intel Corporation. The flow-through gate 242 is preferably a latch, although various other logic gates are within the contemplation of the described embodiments. In addition, the first flip-flop 250, the second flip-flop 222, the third flip-flop 230, and the fourth flip-flop 266 are preferably data flip-flops, although various types of logic gates are within the contemplation of the described embodiments.

One embodiment illustrating operation of the source synchronous address receiver 200 is described with reference to FIGS. 6 and 7. Referring to FIG. 7, a timing diagram 400 is depicted illustrating one embodiment. An address packet 122 (pad) as depicted in FIG. 6 illustrates the first component, or phase zero component 132 (A0), and the second, or phase one component 140 (A1). The enable signal 240 (POLENB) is initially low. Since the flow-through gate 242 is active low enabled, during reset of the enable signal 240, the flow-through gate is enabled or active low, thus making the flow-through gate 242 transparent.

Accordingly, in one embodiment, receiver 200 enables the flow-through path from the address pin 204 to the core logic of the chipset 304 (FIG. 45) for the first component, or phase zero component 132, of the address packet 122. In one embodiment, at the moment the phase zero component 132 of the address packet 122 appears on the address pin 204, the data is immediately made available to the chipset as IFA[0]. Enabling of the flow-through gate 242 is toggled by the falling edge of the digital source synchronous address strobe signal 210 (ABUTFADSTB), thus closing the flow-through gate 242 as indicated by the arrow 402. The flow-through gate 242 is again made transparent by the falling edge of the digital address select signal 208 (ABUTADS), thus enabling the flow-through path for next phase zero address component 132 of the address packet 122 (B0) as indicated by the arrow 404.

The phase one component 140 of the address packet 122 (A1) is sampled at the rising edge of the digital address strobe signal 210 and appears as IFA[1] as indicated by the arrow 406. The digital address select signal 208 (ABUTFADS) is essentially a complement of the flopped address select signal 216 (flopped ADS#) as described with reference to FIG. 6 which is generated from the digital common clock protocol signal 264. Once the phase one component 140 of the address packet 122 is received by the chipset 304 (FIG. 5), the chipset 304 (FIG. 5) can complete decoding of the address packet 122.

In one embodiment, once the address packet is decoded by the chipset 304, the decoded address is provided to the main memory 306 via the memory bus 308 to retrieve the data requested by the CPU 302 and consequently transferred to the CPU 302 as depicted in FIG. 5. Consequently, in one embodiment, a flow-through path achieves a low-latency path between the system bus address input to the memory bus resulting in a high performance memory controller, which can accommodate the increased CPU processing speeds required in today's technology, as well as future processing speeds.

In one embodiment, a source synchronous address receiver provides a low latency path between the host system bus and the memory bus to enable a high performance memory controller. In one embodiment, this low latency path is achieved by using a flow-through path. This flow-through path is controlled by two inputs, one is a source synchronous strobe directing the apparatus to latch an address and store it, while the other is a common clock protocol signal that signals the beginning of the address transfer which enables the flow-through path. This use of source synchronous and common clock signals to achieve the desired end result (minimal latency to the memory address) is unique to the described embodiment. The embodiments described herein may be used in future implementations of source synchronous system address buses and memory controller devices.

Having disclosed exemplary embodiments and the best mode, modifications and variations may be made to the disclosed embodiments while remaining within the scope of the invention as defined by the following claims. 

1. A method comprising: generating an enable signal in response to a digital address strobe signal and a digital address select signal to activate the enable signal prior to receipt of an address packet; and providing a flow-through path from an address pin to a chipset for a first component of the address packet in response to the enable signal, such that the first component of the address packet is provided to the chipset once the address packet appears on the address pin to expedite initiation of decoding of the address packet by the chipset.
 2. The method of claim 1, wherein the generating of the enable signal further comprises: feeding the digital address select signal as a clock pulse input of a first gate including a feed-back inverter coupled between an input and an output of the first gate; feeding the digital address strobe signal as a clock pulse input of a second flip-flop including a feed-back inverter coupled between an input and an output of the second flip-flop; and performing an exclusive-OR operation on an output of the first gate and an output of the second gate to generate the enable signal.
 3. The method of claim 1, wherein the generating of the enable signal further comprises: receiving an analog source synchronous strobe signal on an address strobe pin; and converting the analog address strobe signal to a digital address strobe signal as the digital address strobe signal using a differential amplifier and a reference voltage.
 4. The method of claim 1, wherein the generating of the enable signal, further comprises: receiving an analog common clock protocol signal on an address select pin; converting the analog common clock protocol signal into a digital common clock protocol signal using a differential amplifier and a reference voltage; feeding the digital common clock protocol signal as an input to a first gate and a common clock signal as a clock pulse input of the first gate to generate a flopped address select signal at an output of the first gate; and feeding the flopped address select signal to an input of an inverter to generate the digital address select signal at an output of the inverter.
 5. The method of claim 1, further comprising: deactivating the enable signal in response to the detection of a transition in the digital address strobe signal; and reactivating the enable signal, prior to receipt of a next address packet, in response to the detection of a transition in the digital address select signal.
 6. The method of claim 5, wherein deactivating the enable signal further comprises: detecting a falling signal transition of the digital address strobe signal; and driving the enable signal high to disable the enable signal.
 7. The method of claim 5, wherein reactivating the enable signal further comprises: detecting a falling signal transition of the digital address select signal; and driving the enable signal low to activate the enable signal prior to receipt of the next address packet.
 8. The method of claim 1, wherein the enable signal is an active low signal, such that during reset of the enable signal, the enable signal is active prior to receipt of the address packet.
 9. The method of claim 1, further comprising: providing the second component of the digital address packet to the chipset in response to the digital address strobe signal, such that the chipset can complete decoding of the address packet.
 10. The method of claim 1, wherein prior to providing the flow-through path, the method comprises: receiving an address packet on an address pin for data requested from a processor on a system bus, the address packet having a first component describing a transaction type of the address packet and a second component describing attributes of the address packet.
 11. An address receiver, comprising: a flow-through circuit to generate an enable signal in response to a digital address strobe signal and a digital address select signal to activate the enable signal prior to receipt of an address packet; and a flow-through gate having a digital address packet and the enable signal as inputs, the flow-through gate providing a first component of the digital address packet to a chipset in response to the enable signal once the digital address packet appears on the address pin, thereby providing a flow through path from the address pin to the chipset for the first component of the digital address packet to expedite initiation of decoding of the address packet by the chipset.
 12. The address receiver of claim 11, wherein the flow-through circuit further comprises: a first gate including a feed-back inverter coupled between an input and an output of the first gate and the digital address select signal as a clock pulse input of the first gate; a second gate including a feed-back inverter coupled between an input and an output of the second gate and the digital address strobe signal as a clock pulse input of the second gate; and an exclusive-OR gate having an output of the first gate and an output of the second gate as inputs to generate the enable signal as an output.
 13. The address receiver of claim 11, further comprising: an input differential amplifier to compare an address packet received on an address pin for a data request against a reference voltage and generate a digital address packet, the digital address packet having a first component describing a transaction type of the address packet and a second component describing attributes of the address packet.
 14. The address receiver of claim 11, further comprising: a non flow-through gate having the digital address packet and a digital address strobe signal as inputs and providing the second component of the digital address packet to the chipset in response to the digital address strobe signal, such that the chipset can complete decoding of the address packet.
 15. The address receiver of claim 14, wherein the non flow-through gate is a data flip-flop.
 16. The address receiver of claim 11, further comprising: a first differential amplifier to compare a common clock protocol signal received on an address select pin against a reference voltage and generate a digital common clock protocol signal; a first gate to receive the digital common clock protocol signal as an input and a common clock signal as a clock pulse input and generate a flopped address select signal at an output of the first gate; and an inverter to receive the flopped address select signal and generate the digital address select signal at an output of the inverter for input to the flow-through circuit.
 17. The address receiver of claim 14, wherein the non flow-through gate is a data flip-flop.
 18. The address receiver of claim 11, further comprising: a second differential amplifier to compare an analog address strobe signal received on an address strobe pin against a reference voltage and generate the digital address strobe signal.
 19. The address receiver of claim 11, wherein the flow-through gate is an active low enabled latch.
 20. A memory controller comprising: a chipset coupled to the memory by a memory bus; a system bus coupling a processor to the chipset, the chipset to decode an address packet on the system bus for data requested by the processor from the memory, wherein the system bus includes a source-synchronous address receiver including: a flow-through circuit to generate an enable signal in response to a digital address strobe signal and a digital address select signal to activate the enable signal prior to receipt of an address packet; a flow-through gate having a digital address packet and the enable signal as inputs, the flow-through gate to provide the first component of the digital address packet to a chipset in response to the enable signal once the digital address packet appears on an address pin, thereby providing a flow through path from the address pin to the chipset for the first component of the digital address packet to expedite initiation of decoding of the address packet by the chipset.
 21. The memory controller of claim 20, further comprising: a non flow-through gate having the digital address packet and the digital address strobe signal as inputs and providing the second component of the digital address packet to the chipset in response to the digital address strobe signal, such that the chipset can complete decoding of the address packet.
 22. The memory controller of claim 20, wherein the flow-through circuit further comprises: a first gate including a feed-back inverter coupled between an input and an output of the first gate and the digital address select signal as a clock pulse input of the first gate; a second gate including a feed-back inverter coupled between an input and an output of the second gate and the digital address strobe signal as a clock pulse input of the second gate; and an exclusive-OR gate having an output of the first gate and an output of the second gate as inputs to generate the enable signal as an output.
 23. The memory controller of claim 20, wherein the flow through circuit is to deactivate the enable signal in response to the detection of a transition in the digital address strobe signal and to reactivate the enable signal, prior to receipt of a next address packet, in response to the detection of a transition in the digital address select signal.
 24. The memory controller of claim 20, further comprising: an input differential amplifier to compare the address packet received for the data request on the address pin against a reference voltage and generate a digital address packet, the digital address packet having the first component describing an address transaction type and the second component describing attributes of the address; a first differential amplifier to compare an analog common clock protocol signal received on an address select pin against a reference voltage and generate a digital common clock protocol signal; a first gate to receive the digital common clock protocol signal as an input and a common clock signal as a clock pulse input and generate a flopped address select signal at an output of the first gate; and an inverter to receive the flopped address select signal and generate the digital address select signal at an output of the inverter for input to the flow-through circuit.
 25. The memory controller of claim 24, wherein the first gate is a data flip-flop.
 26. The memory controller of claim 20, further comprising: a second differential amplifier to compare an analog source synchronous strobe signal received on an address strobe pin against a reference voltage and generate the digital address strobe signal.
 27. The memory controller of claim 20, wherein the flow-through gate is an active low enabled latch.
 28. The memory controller of claim 21, wherein the non flow-through gate is a data flip-flop. 